View MT9040_6163480.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 MT9040 t1/e1 synchronizer advance information features supports at&t tr62411 and bellcore gr- 1244-core and stratum 4 timing for ds1 interfaces supports etsi ets 300 011, tbr 4, tbr 12 and tbr 13 timing for e1 interfaces selectable 19.44 mhz, 1.544mhz, 2.048mhz or 8khz input reference signals provides c1.5, c2, c4, c6, c8, c16, and c19 (sts-3/oc3 clock divided by 8) output clock signals provides 5 different styles of 8 khz framing pulses attenuates wander from 1.9hz fast lock mode jtag boundary scan applications synchronization and timing control for multitrunk t1 and e1 systems st-bus clock and frame pulse source description the MT9040 t1/e1 system synchronizer contains a digital phase-locked loop (dpll), which provides timing and synchronization signals for t1 and e1 primary rate transmission links. the MT9040 generates st-bus clock and framing signals that are phase locked to either a 19.44 mhz, 2.048mhz, 1.544mhz, or 8khz input reference. the MT9040 is compliant with at&t tr62411 and bellcore gr-1244-core, stratum 4; and etsi ets 300 011. it will meet the jitter/wander tolerance, jitter transfer, intrinsic jitter, frequency accuracy and capture range for these specifications. figure 1 - functional block diagram ieee 1149.1a feedback control state machine dpll frequency select mux input impairment monitor output interface circuit ms fs1 fs2 tck rst vdd vss c1.5o c19o c2o c4o c8o c16o f0o f8o f16o osco osci master clock tdo tdi tms trst c6o rsp tsp flock lock im ref ds5406 issue 2 january 2001 ordering information MT9040an 48 pin ssop -40 to +85 c
MT9040 advance information 2 figure 2 - pin connections pin description pin # name description 1,10, 23,31 v ss ground. 0 volts. (vss pads). 2 rst reset (input). a logic low at this input resets the MT9040. to ensure proper operation, the device must be reset after reference signal frequency changes and power-up. the rst pin should be held low for a minimum of 300ns. while the rst pin is low, all frame and clock outputs are at logic high. following a reset, the input reference source and output clocks and frame pulses are phase aligned as shown in figure 9. 3,4,5, 38,43 ic internal connection. leave open circuit. 6 ref reference (input). this is the input reference source (falling edge) used for synchronization. one of four possible frequencies (8khz, 1.544mhz, 2.048mhz or 19.44mhz) may be used. 7,17 28,35 v dd positive supply voltage. +3.3v dc nominal. 8 osco oscillator master clock (cmos output). for crystal operation, a 20mhz crystal is connected from this pin to osci, see figure 6. for clock oscillator operation, this pin is left unconnected, see figure 5. 9 osci oscillator master clock (cmos input). for crystal operation, a 20mhz crystal is connected from this pin to osco, see figure 6. for clock oscillator operation, this pin is connected to a clock source, see figure 5. 11 f16o frame pulse st-bus 8.192 mb/s (cmos output). this is an 8khz 61ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st-bus operation at 8.192 mb/s. see figure 10. 12 f0o frame pulse st-bus 2.048mb/s (cmos output). this is an 8khz 244ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st-bus operation at 2.048mb/s and 4.096mb/s. see figure 10. 13 rsp receive sync pulse (cmos output). this is an 8khz 488ns active high framing pulse, which marks the beginning of an st-bus frame. this is typically used for connection to the siemens munich-32 device. see figure 11. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 trst tdi tdo ic ic fs1 fs2 ic ic ic ms vdd ic ic nc vss ic im vdd rst ic ic ref vdd osco osci vss f16o tsp f8o c1.5o c2o c4o c19o 48 tms v ss 21 27 c6o flock 22 26 vss 23 25 c8o ic 24 c16o MT9040an tck rsp f0o ic vdd lock
3 advance information MT9040 14 tsp transmit sync pulse (cmos output). this is an 8khz 488ns active high framing pulse, which marks the beginning of an st-bus frame. this is typically used for connection to the siemens munich-32 device. see figure 11. 15 f8o frame pulse (cmos output). this is an 8khz 122ns active high framing pulse, which marks the beginning of a frame. see figure 10. 16 c1.5o clock 1.544mhz (cmos output). this output is used in t1 applications. 18 lock lock indicator (cmos output). this output goes high when the pll is frequency locked to the input reference. 19 c2o clock 2.048mhz (cmos output). this output is used for st-bus operation at 2.048mb/s. 20 c4o clock 4.096mhz (cmos output). this output is used for st-bus operation at 2.048mb/s and 4.096mb/s. 21 c19o clock 19.44mhz (cmos output). this output is used in oc3/sts3 applications. 22 flock fast lock mode (input). set high to allow the pll to quickly lock to the input reference (less than 500 ms locking time). 24 ic internal connection. tie low for normal operation. 25 c8o clock 8.192mhz (cmos output). this output is used for st-bus operation at 8.192mb/s. 26 c16o clock 16.384mhz (cmos output). this output is used for st-bus operation with a 16.384mhz clock. 27 c6o clock 6.312 mhz (cmos output). this output is used for ds2 applications. 29 im impairment monitor (cmos output). a logic high on this pin indicates that the input impairment monitor has automatically put the device into freerun mode. 30 ic internal connection. tie high for normal operation. 32 nc no connection. leave open circuit . 33,34, 42 ic internal connection. tie low for normal operation. 36 ms mode/control select (input). this input determines the state (normal or freerun) of operation. the logic level at this input is gated in by the rising edge of f8o. see table 2. 37, 39 ic internal connection. tie low for normal operation. 40 fs2 frequency select 2 (input). this input, in conjunction with fs1, selects which of four possible frequencies (8khz, 1.544mhz, 2.048mhz or 19.44mhz) may be input to the ref input. see table 1. 41 fs1 frequency select 1 (input). see pin description for fs2. 44 tdo test serial data out (cmos output). jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag scan is not enabled. 45 tdi test serial data in (input). jtag serial test instructions and data are shifted in on this pin. this pin is internally pulled up to v dd . 46 trst test reset (input). asynchronously initializes the jtag tap controller by putting it in the test- logic-reset state. 47 tck test clock (input). provides the clock to the jtag test logic. 48 tms test mode select (input). jtag signal that controls the state transitions of the tap controller. pin description (continued) pin # name description
MT9040 advance information 4 figure 3 - dpll block diagram control circuit state select from input impairment monitor state select from state machine feedback signal from frequency select mux dpll reference to output interface circuit loop filter digitally controlled oscillator phase detector reference functional description the MT9040 is a t1/e1 trunk synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for t1 and e1 primary rate digital transmission links. figure 1 is a functional block diagram which is described in the following sections. frequency select mux circuit the MT9040 operates on the falling edge of the reference. it operates with one of four possible input reference frequencies (8khz, 1.544mhz, 2.048mhz or 19.44mhz). the frequency select inputs (fs1 and fs2) determine which of the four frequencies may be used at the reference input. a reset ( rst) must be performed after every frequency select input change. see table 1. table 1 - input frequency selection digital phase lock loop (dpll) as shown in figure 3, the dpll of the MT9040 consists of a phase detector, loop filter, digitally controlled oscillator and a control circuit. phase detector - the phase detector compares the reference signal with the feedback signal from the frequency select mux circuit, and provides an error signal corresponding to the phase difference between the two. this error signal is passed to the loop filter. the frequency select mux allows the proper feedback signal to be externally selected (e.g., 8khz, 1.544mhz, 2.048mhz or 19.44mhz). loop filter - the loop filter is similar to a first order low pass filter with a 1.9 hz cutoff frequency for all four reference frequency selections (8khz, 1.544mhz, 2.048mhz or 19.44mhz). this filter ensures that the network jitter transfer requirements are met. control circuit - the control circuit uses status and control information from the state machine and the input impairment circuit to set the mode of the dpll. the two possible modes are normal and freerun. digitally controlled oscillator (dco) - the dco receives the filtered signal from the loop filter, and based on its value, generates a corresponding digital output signal. the synchronization method of the dco is dependent on the state of the MT9040. in normal mode, the dco provides an output signal which is frequency and phase locked to the input reference signal. in freerun mode, the dco is free running with an accuracy equal to the accuracy of the osci 20mhz source. lock indicator - if the pll is in frequency lock (frequency lock means the center frequency of the pll is identical to the line frequency), and the input phase offset is small, then the lock signal will be set high. output interface circuit the output of the dco (dpll) is used by the output interface circuit to provide the output signals shown in figure 4. the output interface circuit uses four tapped delay lines followed by a t1 divider circuit, an e1 divider circuit, and a ds2 divider circuit to generate the required output signals. fs2 fs1 input frequency 0 0 19.44mhz 0 1 8khz 1 0 1.544mhz 1 1 2.048mhz
advance information MT9040 5 four tapped delay lines are used to generate 16.384mhz, 12.352mhz, 12.624mhz and 19.44 mhz signals. the e1 divider circuit uses the 16.384mhz signal to generate four clock outputs and five frame pulse outputs. the c8o, c4o and c2o clocks are generated by simply dividing the c16o clock by two, four and eight respectively. these outputs have a nominal 50% duty cycle. the t1 divider circuit uses the 12.384mhz signal to generate the c1.5o clock by dividing the internal c12 clock by eight. this output has a nominal 50% duty cycle. the ds2 divider circuit uses the 12.624 mhz signal to generate the clock output c6o. this output has a nominal 50% duty cycle. figure 4 - output interface circuit block diagram the frame pulse outputs ( f0o, f8o, f16o, tsp, and rsp) are generated directly from the c16 clock. the t1 and e1 signals are generated from a common dpll signal. consequently, all frame pulse and clock outputs are locked to one another for all operating states, and are also locked to the input reference in normal mode. see figures 9,10 and 11. all frame pulse and clock outputs have limited driving capability, and should be buffered when driving high capacitance (e.g., 30pf) loads. input impairment monitor this circuit monitors the input signal to the dpll for a complete loss of incoming signal, or a large frequency shift in the incoming signal. if the input signal is outside the impairment monitor capture range the pll automatically changes from normal mode to free run mode. see ac electrical characteristics - performance for the impairment monitor capture range. when the incoming signal returns to normal, the dpll is returned to normal mode. master clock the MT9040 can use either a clock or crystal as the master timing source. for recommended master timing circuits, see the applications - master clock section. control and mode of operation the MT9040 has two possible modes of operation, normal and freerun. as shown in table 2, the mode/ control select pin ms selects the mode. normal mode normal mode is typically used when a slave clock source, synchronized to the network is required. in normal mode, the MT9040 provides timing (c1.5o, c2o, c4o, c8o, c16o and c19o) and frame synchronization ( f0o, f8o, f16o, tsp and rsp) signals, which are synchronized to the reference input. the input reference signal may have a nominal frequency of 8khz, 1.544mhz, 2.048mhz or 19.44mhz. from a reset condition, the MT9040 will take up to 30 seconds (see ac electrical characteristics) of input reference signal to output signals which are synchronized (phase locked) to the reference input. tapped delay line from dpll t1 divider e1 divider 16mhz 12mhz c1.5o c2o c4o c8o c16o f0o f8o f16o tapped delay line tapped delay line tapped delay line ds2 divider 12mhz 19mhz c6o c19o rsp tsp ms mode 0 normal 1 freerun table 2 - operating modes and states
MT9040 advance information 6 the reference frequencies are selected by the frequency control pins fs2 and fs1 as shown in table 1. fast lock mode fast lock mode is a submode of normal mode, it is used to allow the MT9040 to lock to a reference more quickly than normal mode will allow. typically, the pll will lock to the incoming reference within 500 ms if the flock pin is set high. freerun mode freerun mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved. in freerun mode, the MT9040 provides timing and synchronization signals which are based on the master clock frequency (osci) only, and are not synchronized to the reference signal. the accuracy of the output clock is equal to the accuracy of the master clock (osci). so if a 32ppm output clock is required, the master clock must also be 32ppm. see applications - crystal and clock oscillator sections. MT9040 measures of performance the following are some synchronizer performance indicators and their corresponding definitions. intrinsic jitter intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. it is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. intrinsic jitter may also be measured when the device is free running by measuring the output jitter of the device. intrinsic jitter is usually measured with various bandlimiting filters depending on the applicable standards. in the MT9040, the intrinsic jitter is limited to less than 0.02ui on the 2.048mhz and 1.544mhz clocks. jitter tolerance jitter tolerance is a measure of the ability of a pll to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. the applied jitter magnitude and jitter frequency depends on the applicable standards. jitter transfer jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. for the MT9040, the jitter attenuation is determined by the 1.9hz low pass loop filter. the MT9040 has twelve outputs with three possible input frequencies (except for 19.44mhz, which is internally divided to 8khz) for a total of 36 possible jitter transfer functions. since all outputs are derived from the same signal, the jitter transfer values for the four cases, 8khz to 8khz, 1.544mhz to 1.544mhz and 2.048mhz to 2.048mhz can be applied to all outputs. it should be noted that 1ui at 1.544mhz is 644ns, which is not equal to 1ui at 2.048mhz, which is 488ns. consequently, a transfer value using different input and output frequencies must be calculated in common units (e.g., seconds) as shown in the following example. what is the t1 and e1 output jitter when the t1 input jitter is 20ui (t1 ui units) and the t1 to t1 jitter attenuation is 18db? using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the three jitter transfer functions provided. note that the resulting jitter transfer functions for all combinations of inputs (8khz, 1.544mhz, 2.048mhz) and outputs (8khz, 1.544mhz, 2.048mhz, 4.096mhz, 8.192mhz, 16.384mhz, 19.44mhz) for a outputt 1 inputt 1 a 20 ------ - ?? ?? 10 = outputt 120 18 20 -------- - ?? ?? 10 2.5 ui t 1 () == outpute 1 outputt 1 644 ns () 488 ns () ------------------- 3.3 ui t 1 () = = outpute 1 outputt 1 1 uit 1 () 1 uie 1 () --------------------- - =
advance information MT9040 7 given input signal (jitter frequency and jitter amplitude) are the same. since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). frequency accuracy frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. for the MT9040, the freerun accuracy is equal to the master clock (osci) accuracy. capture range also referred to as pull-in range. this is the input frequency range over which the synchronizer must be able to pull into synchronization. the MT9040 capture range is equal to 230 ppm minus the accuracy of the master clock (osci). for example, a 32 ppm master clock results in a capture range of 198 ppm. lock range this is the input frequency range over which the synchronizer must be able to maintain synchronization. the lock r ange is equal to the capture range for the MT9040. phase lock time this is the time it takes the synchronizer to phase lock to the input signal. phase lock occurs when the input signal and output signal are not changing in phase with respect to each other (not including jitter). lock time is very difficult to determine because it is affected by many factors which include: i) initial input to output phase difference ii) initial input to output frequency difference iii) synchronizer loop filter although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. for instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. see ac electrical characteristics - performance for maximum phase lock time. MT9040 provides a fast lock pin (flock), which, when set high enables the pll to lock to an incoming reference within approximately 500 ms. MT9040 and network specifications the MT9040 fully meets all applicable pll requirements (intrinsic jitter, jitter/wander tolerance, jitter/wander transfer, frequency accuracy and capture range for the following specifications. 1. bellcore gr-1244-core june 1995 for stratum 4 2. at&t tr62411(ds1) december 1990 for stratum 4 3. ansi t1.101 (ds1) february 1994 for stratum 4 4. etsi 300 011 (e1) april 1992 5. tbr 4 november 1995 6. tbr 12 december 1993 7. tbr 13 january 1996 8. itu-t i.431 march 1993
MT9040 advance information 8 applications this section contains MT9040 application specific details for clock and crystal operation, reset operation, power supply decoupling, and control operation. master clock the MT9040 can use either a clock or crystal as the master timing source. in freerun mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source at the osci pin. for applications not requiring an accurate freerun mode, tolerance of the master timing source may be 100ppm. for applications requiring an accurate freerun mode, such as at&t tr62411, the tolerance of the master timing source must be no greater than 32ppm. another consideration in determining the accuracy of the master timing source is the desired capture range. the sum of the accuracy of the master timing source and the capture range of the MT9040 will always equal 230ppm. for example, if the master timing source is 100ppm, then the capture range will be 130ppm. clock oscillator - when selecting a clock oscillator, numerous parameters must be considered. this includes absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle. figure 5 - clock oscillator circuit for applications requiring 32ppm clock accuracy, the following clock oscillator module may be used. fox f7c-2e3-20.0mhz frequency: 20mhz tolerance: 25ppm 0c to 70c rise & fall time: 10ns (0.33v 2.97v 15pf) duty cycle: 40% to 60% cts cb3lv-5i-20.0 mhz frequency: 20mhz tolerance: 25ppm rise & fall time: 10ns duty cycle: 45% to 55% the output clock should be connected directly (not ac coupled) to the osci input of the MT9040, and the osco output should be left open as shown in figure 8. crystal oscillator - alternatively, a crystal oscillator may be used. a complete oscillator circuit made up of a crystal, resistor and capacitors is shown in figure 6. figure 6 - crystal oscillator circuit the accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. typically, for a 20mhz crystal specified with a 32pf load capacitance, each 1pf change in load capacitance contributes approximately 9ppm to the frequency deviation. consequently, capacitor tolerances, and stray capacitances have a major effect on the accuracy of the oscillator frequency. the trimmer capacitor shown in figure 6 may be used to compensate for capacitive effects. if accuracy is not a concern, then the trimmer may be removed, the 39pf capacitor may be increased to 56pf, and a wider tolerance crystal may be substituted. +3.3v 20mhz out gnd 0.1uf +3.3v osco MT9040 osci no connection osco 56pf 1m ? 39pf 3-50pf 20mhz MT9040 osci 100 ? 1uh 1uh inductor: may improve stability and is optional
advance information MT9040 9 the crystal should be a fundamental mode type - not an overtone. the fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. the crystal specification is as follows. frequency: 20mhz tolerance: as required oscillation mode: fundamental resonance mode: parallel load capacitance: 32pf maximum series resistance: 35 ? approximate drive level: 1mw e.g., r1b23b32-20.0mhz (20ppm absolute, 6ppm 0c to 50c, 32pf, 25 ? ) reset circuit a simple power up reset circuit with about a 50us reset low time is shown in figure 7. resistor r p is for protection only and limits current into the rst pin during power down conditions. the reset low time is not critical but should be greater than 300ns. figure 7 - power-up reset circuit +3.3v rst r p 1k ? c 10nf r 10k ? MT9040
MT9040 advance information 10 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. * supply voltage and operating temperature are as per recommended operating conditions. absolute maximum ratings* - voltages are with respect to ground (v ss ) unless otherwise stated. parameter symbol min max units 1 supply voltage v dd -0.5 5.0 v 2 voltage on any pin v pin -.05 v dd +0.5 v 3 current on any pin i pin -0.5 30 ma 4 storage temperature t st -55 125 c 5 48 ssop package power dissipation p pd 200 mw recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min max units 1 supply voltage v dd 3.0 3.6 v 2 operating temperature t a -40 85 c dc electrical characteristics* - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min max units conditions/notes 1 supply current with: osci = 0v i dds 1.8 ua outputs unloaded 2 osci = clock i dd 50 ma outputs unloaded 3 cmos high-level input voltage v cih 0.7v dd v osci 4 cmos low-level input voltage v cil 0.3v dd v osci 5 input leakage current i il 15 av i =v dd or 0v 6 high-level output voltage v oh 2.4 v i oh = 10 ma 7 low-level output voltage v ol 0.4 v i ol = 10 ma
11 advance information MT9040 ? see "notes" following ac electrical characteristics tables. * supply voltage and operating temperature are as per recommended operating conditions. * timing for input and output signals is based on the worst case result of the cmos thresholds. * see figure 8. figure 8 - timing parameter measurement voltage levels ac electrical characteristics - performance characteristics sym min max units conditions/ notes? 1 freerun mode accuracy with osci at: 0ppm -0 +0 ppm 4-8 2 32ppm -32 +32 ppm 4-8 3 100ppm -100 +100 ppm 4-8 4 capture range with osci at: 0ppm -230 +230 ppm 1-3,5-8 5 32ppm -198 +198 ppm 1-3,5-8 6 100ppm -130 +130 ppm 1-3,5-8 7 phase lock time 30 s 1-3,5-14 8 impairment monitor capture range at: 8khz, 19.44mhz -18k +18k ppm 1-3,5,8,9-11 9 1.544mhz -36k +36k ppm 1-3,6,9-11 10 2.048mhz -36k +36k ppm 1-3,7,9-11 ac electrical characteristics - timing parameter measurement voltage levels* - voltages are with respect to ground (v ss ) unless otherwise stated characteristics sym cmos units 1 threshold voltage v t 0.5v dd v 2 rise and fall threshold voltage high v hm 0.7v dd v 3 rise and fall threshold voltage low v lm 0.3v dd v t irf, t orf timing reference points all signals v hm v t v lm t irf, t orf
MT9040 advance information 12 ac electrical characteristics - input/output timing characteristics sym min max units 1 reference input pulse width high or low t rw 100 ns 2 reference input rise or fall time t irf 10 ns 3 8khz reference input to f8o delay t r8d -21 6 ns 4 1.544mhz reference input to f8o delay t r15d 337 363 ns 5 2.048mhz reference input to f8o delay t r2d 222 238 ns 6 19.44mhz reference input to f8o delay t r19d 46 57 ns 7 f8o to f0o delay t f0d 111 130 ns 8 f16o setup to c16o f alling t f16s 25 40 ns 9 f16o hold to c16o r ising t f16h -10 10 ns 10 f8o to c1.5o delay t c15d -45 -25 ns 11 f8o to c6o delay t c6d -10 10 ns 12 f8o to c2o delay t c2d -11 5 ns 13 f8o to c4o delay t c4d -11 5 ns 14 f8o to c8o delay t c8d -11 5 ns 15 f8o to c16o delay t c16d -11 5 ns 16 f8o to tsp delay t tspd -6 10 ns 17 f8o to rsp delay t rspd -8 8 ns 18 f8o to c19o delay t c19d -15 5 ns 19 c1.5o pulse width high or low t c15w 309 339 ns 20 c6o pulse width high or low t c6w 70 86 ns 21 c2o pulse width high or low t c2w 230 258 ns 22 c4o pulse width high or low t c4w 111 133 ns 23 c8o pulse width high or low t c8w 52 70 ns 24 c16o pulse width high or low t c16wl 24 35 ns 25 tsp pulse width high t tspw 478 494 ns 26 rsp pulse width high t rspw 474 491 ns 27 c19o pulse width high t c19wh 25 35 ns 28 c19o pulse width low t c19wl 17 25 ns 29 f0o pulse width low t f0wl 234 254 ns 30 f8o pulse width high t f8wh 109 135 ns 31 f16o pulse width low t f16wl 47 75 ns 32 output clock and frame pulse rise or fall time t orf 9ns 33 input controls setup time t s 100 ns 34 input controls hold time t h 100 ns
13 advance information MT9040 figure 9 - input to output timing (normal mode) figure 10 - output timing 1 t rw t r15d t r2d t r8d v t v t v t v t ref 8khz ref 2.048mhz ref 1.544mhz t rw t rw ref 19.44mhz v t f8o t rw t r19d notes: 1. input to output delay values are valid after a rst with no further state changes t f16wl t f8wh t c15w t c15d t c4d t c16d t c8d t f0d f0o f16o c16o c8o c4o c2o c1.5o t c2d f8o t c4w t f0wl t c16wl t c8w t c2w t c8w t c4w v t v t v t v t v t v t v t v t t c19wl c19o t c19d t c6d t c6w t c6w c6o t c19wh v t v t t f16h t f16s
MT9040 advance information 14 figure 11 - output timing 2 figure 12 - input controls setup and hold timing ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - intrinsic jitter un?tered characteristics sym max units conditions/notes? 1 intrinsic jitter at f8o (8khz) 0.0002 uipp 1-12,19-22,26 2 intrinsic jitter at f0o (8khz) 0.0002 uipp 1-12,19-22,26 3 intrinsic jitter at f16o (8khz) 0.0002 uipp 1-12,19-22,26 4 intrinsic jitter at c1.5o (1.544mhz) 0.030 uipp 1-12,19-22,27 5 intrinsic jitter at c2o (2.048mhz) 0.040 uipp 1-12,19-22,28 6 intrinsic jitter at c6o (6.312mhz) 0.120 uipp 1-12,19-22,29 7 intrinsic jitter at c4o (4.096mhz) 0.080 uipp 1-12,19-22,30 8 intrinsic jitter at c8o (8.192mhz) 0.104 uipp 1-12,19-22,31 9 intrinsic jitter at c16o (16.384mhz) 0.104 uipp 1-12,19-22,32 10 intrinsic jitter at tsp (8khz) 0.0002 uipp 1-12,19-22,26 11 intrinsic jitter at rsp (8khz) 0.0002 uipp 1-12,19-22,26 12 intrinsic jitter at c19o (19.44mhz) 0.27 uipp 1-12,19-22,33 t rspd t tspd tsp c2o t tspw t rspw v t v t v t v t rsp f8o t h t s f8o ms1,2, rsel, pcci v t v t
15 advance information MT9040 ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - c1.5o (1.544mhz) intrinsic jitter filtered characteristics sym min max units conditions/notes ? 1 intrinsic jitter (4hz to 100khz ?ter) 0.015 uipp 1-12,19-22,27 2 intrinsic jitter (10hz to 40khz ?ter) 0.010 uipp 1-12,19-22,27 3 intrinsic jitter (8khz to 40khz ?ter) 0.010 uipp 1-12,19-22,27 4 intrinsic jitter (10hz to 8khz ?ter) 0.005 uipp 1-12,19-22,27 ac electrical characteristics - c2o (2.048mhz) intrinsic jitter filtered characteristics sym min max units conditions/notes ? 1 intrinsic jitter (4hz to 100khz ?ter) 0.015 uipp 1-12,19-22,28 2 intrinsic jitter (10hz to 40khz ?ter) 0.010 uipp 1-12,19-22,28 3 intrinsic jitter (8khz to 40khz ?ter) 0.010 uipp 1-12,19-22,28 4 intrinsic jitter (10hz to 8khz ?ter) 0.005 uipp 1-12,19-22,28 ac electrical characteristics - 8khz input to 8khz output jitter transfer characteristics sym min max units conditions/notes ? 1 jitter attenuation for 1hz@0.01uipp input 0 6 db 1,3,7-12, 19-20, 22, 26, 34 2 jitter attenuation for 1hz@0.54uipp input 6 16 db 1,3,7-12, 19-20, 22, 26, 34 3 jitter attenuation for 10hz@0.10uipp input 12 22 db 1,3,7-12, 19-20, 22, 26, 34 4 jitter attenuation for 60hz@0.10uipp input 28 38 db 1,3,7-12, 19-20, 22, 26, 34 5 jitter attenuation for 300hz@0.10uipp input 42 db 1,3,7-12, 19-20, 22, 26, 34 6 jitter attenuation for 3600hz@0.005uipp input 45 db 1,3,7-12, 19-20, 22, 26, 34
MT9040 advance information 16 ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - 1.544mhz input to 1.544mhz output jitter transfer characteristics sym min max units conditions/notes ? 1 jitter attenuation for 1hz@20uipp input 0 6 db 1,4,7-12, 19-20,22,27,34 2 jitter attenuation for 1hz@104uipp input 6 16 db 1,4,7-12, 19-20,22,27,34 3 jitter attenuation for 10hz@20uipp input 12 22 db 1,4,7-12, 19-20,22,27,34 4 jitter attenuation for 60hz@20uipp input 28 38 db 1,4,7-12, 19-20,22,27,34 5 jitter attenuation for 300hz@20uipp input 42 db 1,4,7-12, 19-20,22,27,34 6 jitter attenuation for 10khz@0.3uipp input 45 db 1,4,7-12, 19-20,22,27,34 7 jitter attenuation for 100khz@0.3uipp input 45 db 1,4,7-12, 19-20,22,27,34 ac electrical characteristics - 2.048mhz input to 2.048mhz output jitter transfer characteristics sym min max units conditions/notes ? 1 jitter at output for 1hz@3.00uipp input with 40hz to 100khz ?ter 2.9 uipp 1,5,7-12,19-20, 22,28,34 2 0.09 uipp 1,5,7-12,19-20, 22,28,35 3 jitter at output for 3hz@2.33uipp input with 40hz to 100khz ?ter 1.3 uipp 1,5,7-12,19-20, 22,28,34 4 0.10 uipp 1,5,7-12,19-20, 22,28,35 5 jitter at output for 5hz@2.07uipp input with 40hz to 100khz ?ter 0.80 uipp 1,5,7-12,19-20, 22,28,34 6 0.10 uipp 1,5,7-12,19-20, 22,28,35 7 jitter at output for 10hz@1.76uipp input with 40hz to 100khz ?ter 0.40 uipp 1,5,7-12,19-20, 22,28,34 8 0.10 uipp 1,5,7-12,19-20, 22,28,35 9 jitter at output for 100hz@1.50uipp input with 40hz to 100khz ?ter 0.06 uipp 1,5,7-12,19-20, 22,28,34 10 0.05 uipp 1,5,7-12,19-20, 22,28,35 11 jitter at output for 2400hz@1.50uipp input with 40hz to 100khz ?ter 0.04 uipp 1,5,7-12,19-20, 22,28,34 12 0.03 uipp 1,5,7-12,19-20, 22,28,35 13 jitter at output for 100khz@0.20uipp input with 40hz to 100khz ?ter 0.04 uipp 1,5,7-12,19-20, 22,28,34 14 0.02 uipp 1,5,7-12,19-20, 22,28,33
17 advance information MT9040 ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ? see "notes" following ac electrical characteristics tables. ac electrical characteristics - 8khz input jitter tolerance characteristics sym min max units conditions/notes ? 1 jitter tolerance for 1hz input 0.80 uipp 1,3,7 -12,19-20,22-24,26 2 jitter tolerance for 5hz input 0.70 uipp 1,3,7 -12,19-20,22-24,26 3 jitter tolerance for 20hz input 0.60 uipp 1,3,7 -12,19-20,22-24,26 4 jitter tolerance for 300hz input 0.20 uipp 1,3,7 -12,19-20,22-24,26 5 jitter tolerance for 400hz input 0.15 uipp 1,3,7 -12,19-20,22-24,26 6 jitter tolerance for 700hz input 0.08 uipp 1,3,7 -12,19-20,22-24,26 7 jitter tolerance for 2400hz input 0.02 uipp 1,3,7 -12,19-20,22-24,26 8 jitter tolerance for 3600hz input 0.01 uipp 1,3,7 -12,19-20,22-24,26 ac electrical characteristics - 1.544mhz input jitter tolerance characteristics sym min max units conditions/notes ? 1 jitter tolerance for 1hz input 150 uipp 1,4,7-12,19-20,22-24,27 2 jitter tolerance for 5hz input 140 uipp 1,4,7-12,19-20,22-24,27 3 jitter tolerance for 20hz input 130 uipp 1,4,7-12,19-20,22-24,27 4 jitter tolerance for 300hz input 35 uipp 1,4,7-12,19-20,22-24,27 5 jitter tolerance for 400hz input 25 uipp 1,4,7-12,19-20,22-24,27 6 jitter tolerance for 700hz input 15 uipp 1,4,7-12,19-20,22-24,27 7 jitter tolerance for 2400hz input 4 uipp 1,4,7-12,19-20,22-24,27 8 jitter tolerance for 10khz input 1 uipp 1,4,7-12,19-20,22-24,27 9 jitter tolerance for 100khz input 0.5 uipp 1,4,7-12,19-20,22-24,27 ac electrical characteristics - 2.048mhz input jitter tolerance characteristics sym min max units conditions/notes ? 1 jitter tolerance for 1hz input 150 uipp 1,5,7 -12,19-20,22-24,28 2 jitter tolerance for 5hz input 140 uipp 1,5,7 -12,19-20,22-24,28 3 jitter tolerance for 20hz input 130 uipp 1,5,7 -12,19-20,22-24,28 4 jitter tolerance for 300hz input 50 uipp 1,5,7 -12,19-20,22-24,28 5 jitter tolerance for 400hz input 40 uipp 1,5,7 -12,19-20,22-24,28 6 jitter tolerance for 700hz input 20 uipp 1,5,7 -12,19-20,22-24,28 7 jitter tolerance for 2400hz input 5 uipp 1,5,7 -12,19-20,22-24,28 8 jitter tolerance for 10khz input 1 uipp 1,5,7 -12,19-20,22-24,28 9 jitter tolerance for 100khz input 1 uipp 1,5,7 -12,19-20,22-24,28
MT9040 advance information 18 ? see "notes" following ac electrical characteristics tables. ? notes: voltages are with respect to ground (v ss ) unless otherwise stated. supply voltage and operating temperature are as per recommended operating conditions. timing parameters are as per ac electrical characteristics - timing parameter measurement voltage levels 1. normal mode selected. 2. freerun mode selected. 3. 8khz frequency mode selected. 4. 1.544mhz frequency mode selected. 5. 2.048mhz frequency mode selected. 6. 19.44mhz frequency mode selected. 7. master clock input osci at 20mhz 0ppm. 8. master clock input osci at 20mhz 32ppm. 9. master clock input osci at 20mhz 100ppm. 10. reference input at 0ppm. 11. reference input at 32ppm. 12. reference input at 100ppm. 13. for freerun mode of 0ppm. 14. for freerun mode of 32ppm. 15. for freerun mode of 100ppm. 16. for capture range of 230ppm. 17. for capture range of 198ppm. 18. for capture range of 130ppm. 19. 25pf capacitive load. 20. osci master clock jitter is less than 2nspp, or 0.04uipp where1uipp=1/20mhz. 21. jitter on reference input is less than 7nspp. 22. applied jitter is sinusoidal. 23. minimum applied input jitter magnitude to regain synchronization. 24. loss of synchronization is obtained at slightly higher input jitter amplitudes. 25. within 10ms of the state, reference or input change. 26. 1uipp = 125us for 8khz signals. 27. 1uipp = 648ns for 1.544mhz signals. 28. 1uipp = 488ns for 2.048mhz signals. 29. 1uipp = 158ns for 6.312mhz signals. 30. 1uipp = 244ns for 4.096mhz signals. 31. 1uipp = 122ns for 8.192mhz signals. 32. 1uipp = 61ns for 16.384mhz signals. 33. 1uipp = 51.44ns for 19.44mhz signals. 34. no filter. 35. 40hz to 100khz bandpass filter. 36. with respect to reference input signal frequency. 37. after a rst. 38. master clock duty cycle 40% to 60%. ac electrical characteristics - osci 20mhz master clock input characteristics sym min max units conditions/notes ? 1 tolerance -0 +0 ppm 13,16 2 -32 +32 ppm 14,17 3 -100 +100 ppm 15,18 4 duty cycle 40 60 % 5 rise time 10 ns 6 fall time 10 ns
package outlines small shrink outline package (ssop) - n suf?x pin 1 a 1 b e d e a l h c a 2 dim 20-pin 24-pin 28-pin 48-pin min max min max min max min max a 0.079 (2) - 0.079 (2) 0.079 (2) 0.095 (2.41) 0.110 (2.79) a 1 0.002 (0.05) 0.002 (0.05) 0.002 (0.05) 0.008 (0.2) 0.016 (0.406) b 0.0087 (0.22) 0.013 (0.33) 0.0087 (0.22) 0.013 (0.33) 0.0087 (0.22) 0.013 (0.33) 0.008 (0.2) 0.0135 (0.342) c 0.008 (0.21) 0.008 (0.21) 0.008 (0.21) 0.010 (0.25) d 0.27 (6.9) 0.295 (7.5) 0.31 (7.9) 0.33 (8.5) 0.39 (9.9) 0.42 (10.5) 0.62 (15.75) 0.63 (16.00) e 0.2 (5.0) 0.22 (5.6) 0.2 (5.0) 0.22 (5.6) 0.2 (5.0) 0.22 (5.6) 0.291 (7.39) 0.299 (7.59) e 0.025 bsc (0.635 bsc) 0.025 bsc (0.635 bsc) 0.025 bsc (0.635 bsc) 0.025 bsc (0.635 bsc) a 2 0.065 (1.65) 0.073 (1.85) 0.065 (1.65) 0.073 (1.85) 0.065 (1.65) 0.073 (1.85) 0.089 (2.26) 0.099 (2.52) h 0.29 (7.4) 0.32 (8.2) 0.29 (7.4) 0.32 (8.2) 0.29 (7.4) 0.32 (8.2) 0.395 (10.03) 0.42 (10.67) l 0.022 (0.55) 0.037 (0.95) 0.022 (0.55) 0.037 (0.95) 0.022 (0.55) 0.037 (0.95) 0.02 (0.51) 0.04 (1.02) notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) ref. jedec standard m0-150/m0118 for 48 pin 5) a & b maximum dimensions include allowable mold flash general-11
m mitel (design) and st-bus are registered trademarks of mitel corporation mitel semiconductor is an iso 9001 registered company copyright 1999 mitel corporation all rights reserved printed in canada technical documen t a tion - n o t for resale world headquarters - canada tel: +1 (613) 592 2122 fax: +1 (613) 592 6909 north america asia/paci?c europe, middle east, tel: +1 (770) 486 0194 tel: +65 333 6193 and africa (emea) fax: +1 (770) 631 8213 fax: +65 333 6192 tel: +44 (0) 1793 518528 fax: +44 (0) 1793 518581 http://www.mitelsemi.com information relating to products and services furnished herein by mitel corporation or its subsidiaries (collectively mitel) is believed to be reliable. however, mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by mitel or licensed from third parties by mitel, whatsoever. purchasers of products are also hereby noti?ed that the use of product in certain ways or in combination with mitel, or non-mitel furnished goods or services may infringe patents or other intellectual property rights owned by mitel. this publication is issued to provide information only and (unless agreed by mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, their speci?cations, services and other information appearing in this publication are subject to change by mitel without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speci?c piece of equipment. it is the users responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in signi?cant injury or death to the user. all products and materials are sold and services provided subject to mitels conditions of sale which are available on request.

▲Up To Search▲

Price & Availability of MT9040

	To Download MT9040 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .